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rev. 0.51 10/06 copyright ? 2006 by silicon laboratori es si8440/41/42/45 si8440/41/42/45 q uad -c hannel d igital i solator features applications safety regulatory approvals description silicon lab's family of digital isol ators are cmos devices that employ an rf coupler to transmit digital information across an isolation barrier. very high speed operation at low power levels is achieved. these parts are available in a 16-pin wide body soic package. three speed grade options (1, 10, 150 mbps) are available and achieve typical propagation delay of less than 10 ns. block diagram high-speed operation: dc ? 150 mbps low propagation delay: <10 ns wide operating supply voltage: 2.375?5.5 v low power: i1 + i2 < 12 ma/channel at 100 mbps precise timing: 2 ns pulse width distortion 1 ns channel-channel matching 2 ns pulse width skew 2500 v rms isolation transient immunity: >25 kv/s tri-state outputs with enable control dc correct no start-up init ialization required <10 s startup time high temperature operation: 125 c at 100 mbps 100 c at 150 mbps wide body soic-16 package isolated switch mode supplies isolated adc, dac motor control power factor correction systems ul recognition:2500 v rms for 1 minute per ul1577 csa component acceptance notice #5a vde certification conformity din en 60747-5-2 (vde0884 part 2):2003-01 din en60950(vde0805): 2001-12;en60950:2000 v iorm = 560 v peak si8441 si8442 b1 a1 a3 a4 a2 b3 b4 b2 si8440/45 a1 a3 a4 a2 b3 b4 b2 b1 a1 a3 a4 a2 b3 b4 b2 b1 nc en1 en1 en2/nc en2 en2 pin assignments wide body soic v dd1 gnd1 a1 a3 a4 en1/nc gnd1 a2 1 2 3 4 5 6 7 8 top view v dd2 gnd2 b2 b1 b4 b3 gnd2 en2/nc 9 12 11 10 13 14 15 16
si8440/41/42/45 2 rev. 0.51
si8440/41/42/45 rev. 0.51 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3. application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.1. theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2. eye diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 4. layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1. supply bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2. input and output characte ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3. enable inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4. rf immunity and comm on mode transient im munity . . . . . . . . . . . . . . . . . . . . . . . 22 4.5. rf radiated emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7. package outline: wide body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
si8440/41/42/45 4 rev. 0.51 1. electrical specifications table 1. electrical characteristics (v dd1 = 5 v, v dd2 = 5 v, t a = ?40 to 125 oc) parameter symbol test condition min typ max unit high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0.8v high level output voltage v oh loh = ?4 ma v dd1 ,v dd2 ?0.4 4.8 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ??10a enable input high current i enh v enx = v ih ?4?a enable input low current i enl v enx = v il ?20?a dc supply current (all inputs 0 v or at supply) si8440/45-a,-b,-c, v dd1 all inputs 0 dc ? 8 12 ma si8440/45-a,-b,-c, v dd2 all inputs 0 dc ? 7 12 ma si8440/45-a,-b,-c, v dd1 all inputs 1 dc ? 15 22 ma si8440/45-a,-b,-c, v dd2 all inputs 1 dc ? 7 12 ma si8441-a,-b,-c, v dd1 all inputs 0 dc ? 9 14 ma si8441-a,-b,-c, v dd2 all inputs 0 dc ? 11 17 ma si8441-a,-b,-c, v dd1 all inputs 1 dc ? 14 21 ma si8441-a,-b,-c, v dd2 all inputs 1 dc ? 13 19 ma si8442-a,-b,-c, v dd1 all inputs 0 dc ? 10 15 ma si8442-a,-b,-c, v dd2 all inputs 0 dc ? 10 15 ma si8442-a,-b,-c, v dd1 all inputs 1 dc ? 13 20 ma si8442-a,-b,-c, v dd2 all inputs 1 dc ? 13 20 ma 10 mbps supply current (all inputs = 5 mhz square wa ve, ci = 15 pf on all outputs) si8440/45-b,-c, v dd1 ?1117ma si8440/45-b,-c, v dd2 ?1015ma si8441-b,-c, v dd1 ?1218ma si8441-b,-c, v dd2 ?1420ma si8442-b,-c, v dd1 ?1318ma si8442-b,-c, v dd2 ?1318ma 100 mbps supply current (all inputs = 50 mhz square wave, ci = 15 pf on all outputs) si8440-c, v dd1 ?1217ma si8440-c, v dd2 ?2732ma si8441-c, v dd1 ?1623ma si8441-c, v dd2 ?2734ma si8442-c, v dd1 ?2229ma si8442-c, v dd2 ?2229ma
si8440/41/42/45 rev. 0.51 5 timing charac teristics si844x-a maximum data rate 0 ? 1 mbps minimum pulse width ? ? 1000 ns propagation delay 1 t phl , t plh 25 40 75 ns pulse width distortion |t plh - t phl | 1 pwd ? ? 30 ns propagation delay skew 2 t psk ? ? 50 ns channel-channel skew 3 t pskcd/od ? ? 40 ns si844x-b maximum data rate 0 ? 10 mbps minimum pulse width ? ? 100 ns propagation delay 1 t phl , t plh 10 20 35 ns pulse width distortion |t plh - t phl | 1 pwd ? ? 7.5 ns propagation delay skew 2 t psk ? ? 25 ns channel-channel skew 3 t pskcd/od ??5ns si844x-c maximum data rate 0 ? 150 mbps minimum pulse width ? ? 6.6 ns propagation delay 1 t phl , t plh 46.59.5ns pulse width distortion |t plh - t phl | 1 pwd ? ? 3 ns propagation delay skew 2 t psk ??5.5ns channel-channel skew 3 t pskcd/od ??3ns table 1. electrical characteristics (continued) (v dd1 = 5 v, v dd2 = 5 v, t a = ?40 to 125 oc) parameter symbol test condition min typ max unit
si8440/41/42/45 6 rev. 0.51 for all models output rise time c1 = 15 pf ? 2 ? ns output fall time c1 = 15 pf ? 2 ? ns common mode transient immunity at logic low output 4 cm l 25 30 ? kv/s common mode transient immunity at logic high output 4 cm h 25 30 ? kv/s enable to data valid t en1 ?5?ns enable to data tri-state t en2 ?5?ns start-up time 5 t su ?3?s notes: 1. t phl propagation delay is measured from th e 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 2. t psk is the magnitude of the worst-case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the reco mmended operating conditions. 3. codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. opposing-directional channel-to-channel matching is the absolute value of the difference in propagation dela ys between any two channels with inputs on opposing sides of the isolation barrier. 4. cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common-mode voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common- mode voltage slew rates apply to both rising and falling co mmon-mode voltage edges. the transient magnitude is the range over which the common mode is slewed. 5. start-up time is the time period from the applic ation of power to valid data at the output. table 1. electrical characteristics (continued) (v dd1 = 5 v, v dd2 = 5 v, t a = ?40 to 125 oc) parameter symbol test condition min typ max unit figure 1. enable timing diagram figure 2. propagation delay timing enable outputs t en1 t en2 input (v ix ) output (v ox ) t plh t phl 50% 50%
si8440/41/42/45 rev. 0.51 7 table 2. electrical characteristics (v dd1 = 3.3 v, v dd2 = 3.3 v, t a = ?40 to 125 oc) parameter symbol test condition min typ max unit high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0.8v high level output voltage v oh loh = ?4 ma v dd1 ,v dd2 ?0.4 3.1 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ??10a enable input high current i enh v enx = v ih ?4?a enable input low current i enl v enx = v il ?20?a dc supply current (all inputs 0 v or at supply) si8440/45-a,-b,-c, v dd1 all inputs 0 dc ? 7 12 ma si8440/45-a,-b,-c, v dd2 all inputs 0 dc ? 7 12 ma si8440/45-a,-b,-c, v dd1 all inputs 1 dc ? 14 21 ma si8440/45-a,-b,-c, v dd2 all inputs 1 dc ? 6 11 ma si8441-a,-b,-c, v dd1 all inputs 0 dc ? 8 13 ma si8441-a,-b,-c, v dd2 all inputs 0 dc ? 11 17 ma si8441-a,-b,-c, v dd1 all inputs 1 dc ? 13 20 ma si8441-a,-b,-c, v dd2 all inputs 1 dc ? 12 18 ma si8442-a,-b,-c, v dd1 all inputs 0 dc ? 9 14 ma si8442-a,-b,-c, v dd2 all inputs 0 dc ? 9 14 ma si8442-a,-b,-c, v dd1 all inputs 1 dc ? 12 18 ma si8442-a,-b,-c, v dd2 all inputs 1 dc ? 12 18 ma 10 mbps supply current (all inputs = 5 mhz square wave, ci = 15 pf on all outputs) si8440/45-b,-c, v dd1 ?1116ma si8440/45-b,-c, v dd2 ?913ma si8441-b,-c, v dd1 ?1117ma si8441-b,-c, v dd2 ?1319ma si8442-b,-c, v dd1 ?1217ma si8442-b,-c, v dd2 ?1217ma 100 mbps supply current (all inputs = 50 mhz square wave, ci = 15 pf on all outputs) si8440-c, v dd1 ?1117ma si8440-c, v dd2 ?1925ma si8441-c, v dd1 ?1320ma si8441-c, v dd2 ?2127ma si8442-c, v dd1 ?1823ma si8442-c, v dd2 ?1823ma
si8440/41/42/45 8 rev. 0.51 timing characteristics si844x-a maximum data rate 0 ? 1 mbps minimum pulse width ? ? 1000 ns propagation delay 1 t phl ,t plh 25 40 75 ns pulse width distortion |t plh - t phl | 1 pwd ? ? 30 ns propagation delay skew 2 t psk ? ? 50 ns channel-channel skew 3 t pskcd/od ? ? 40 ns si844x-b maximum data rate 0 ? 10 mbps minimum pulse width ? ? 100 ns propagation delay 1 t phl , t plh 10 20 35 ns pulse width distortion |t plh - t phl | 1 pwd ? ? 7.5 ns propagation delay skew 2 t psk ? ? 25 ns channel-channel skew 3 t pskcd/od ??5ns si844x-c maximum data rate 0 ? 150 mbps minimum pulse width ? ? 6.6 ns propagation delay 1 t phl , t plh 46.59.5ns pulse width distortion |t plh - t phl | 1 pwd ? ? 3 ns propagation delay skew 2 t psk ??5.5ns channel-channel skew 3 t pskcd/od ??3ns table 2. electrical characteristics (continued) (v dd1 = 3.3 v, v dd2 = 3.3 v, t a = ?40 to 125 oc) parameter symbol test condition min typ max unit
si8440/41/42/45 rev. 0.51 9 for all models output rise time c1 = 15 pf ? 2 ? ns output fall time c1 = 15 pf ? 2 ? ns common mode transient immunity at logic low output 4 cm l 25 30 ? kv/s common mode transient immunity at logic high output 4 cm h 25 30 ? kv/s enable to data valid t en1 ?5?ns enable to data tri-state t en2 ?5?ns start-up time 5 t su ?3?s notes: 1. t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 2. t psk is the magnitude of the worst-case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 3. codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. opposing-directional c hannel-to-channel matching is the absolute value of the difference in propagation delays between any two chan nels with inputs on opposing sides of the isolation barrier. 4. cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common-mode voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew rates apply to both rising and falling common -mode voltage edges. the transient magnitude is the range over which the common mode is slewed. 5. start-up time is the time period from the a pplication of power to valid data at the output. table 2. electrical characteristics (continued) (v dd1 = 3.3 v, v dd2 = 3.3 v, t a = ?40 to 125 oc) parameter symbol test condition min typ max unit
si8440/41/42/45 10 rev. 0.51 table 3. electrical characteristics (v dd1 = 2.5 v, v dd2 = 2.5 v, t a = ?40 to 100 oc) parameter symbol test condition min typ max unit high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0.8v high level output voltage v oh loh = ?4 ma v dd1 ,v dd2 ?0.4 2.3 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ??10a enable input high current i enh v enx = v ih ?4?a enable input low current i enl v enx = v il ?20?a dc supply current (all inputs 0 v or at supply) si8440/45-a,-b,-c, v dd1 all inputs 0 dc ? 7 10 ma si8440/45-a,-b,-c, v dd2 all inputs 0 dc ? 6 10 ma si8440/45-a,-b,-c, v dd1 all inputs 1 dc ? 13 17 ma si8440/45-a,-b,-c, v dd2 all inputs 1 dc ? 6 10 ma si8441-a,-b,-c, v dd1 all inputs 0 dc ? 8 11 ma si8441-a,-b,-c, v dd2 all inputs 0 dc ? 10 12 ma si8441-a,-b,-c, v dd1 all inputs 1 dc ? 12 15 ma si8441-a,-b,-c, v dd2 all inputs 1 dc ? 11 14 ma si8442-a,-b,-c, v dd1 all inputs 0 dc ? 9 12 ma si8442-a,-b,-c, v dd2 all inputs 0 dc ? 9 12 ma si8442-a,-b,-c, v dd1 all inputs 1 dc ? 12 15 ma si8442-a,-b,-c, v dd2 all inputs 1 dc ? 12 15 ma 10 mbps supply current (all inputs = 5 mhz square wave, ci = 15 pf on all outputs) si8440/45-b,-c, v dd1 ?1012ma si8440/45-b,-c, v dd2 ?812ma si8441-b,-c, v dd1 ?1113ma si8441-b,-c, v dd2 ?1215ma si8442-b,-c, v dd1 ?1114ma si8442-b,-c, v dd2 ?1114ma 100 mbps supply current (all inputs = 50 mhz square wave, ci = 15 pf on all outputs) si8440-c, v dd1 ?1113ma si8440-c, v dd2 ?1620ma si8441-c, v dd1 ?1316ma si8441-c, v dd2 ?1721ma si8442-c, v dd1 ?1518ma si8442-c, v dd2 ?1518ma
si8440/41/42/45 rev. 0.51 11 timing characteristics si844x-a maximum data rate 0 ? 1 mbps minimum pulse width ? ? 1000 ns propagation delay 1 t phl ,t plh 25 40 75 ns pulse width distortion |t plh - t phl | 1 pwd ? ? 30 ns propagation delay skew 2 t psk ? ? 50 ns channel-channel skew 3 t pskcd/od ? ? 40 ns si844x-b maximum data rate 0 ? 10 mbps minimum pulse width ? ? 100 ns propagation delay 1 t phl , t plh 10 20 35 ns pulse width distortion |t plh - t phl | 1 pwd ? ? 7.5 ns propagation delay skew 2 t psk ? ? 25 ns channel-channel skew 3 t pskcd/od ??5ns si844x-c maximum data rate 0 ? 100 mbps minimum pulse width ? ? 10 ns propagation delay 1 t phl , t plh 51017ns pulse width distortion |t plh - t phl | 1 pwd ? ? 7 ns propagation delay skew 2 t psk ? ? 12 ns channel-channel skew 3 t pskcd/od ??4ns table 3. electrical characteristics (continued) (v dd1 = 2.5 v, v dd2 = 2.5 v, t a = ?40 to 100 oc) parameter symbol test condition min typ max unit
si8440/41/42/45 12 rev. 0.51 for all models output rise time c1 = 15 pf ? 2 ? ns output fall time c1 = 15 pf ? 2 ? ns common mode transient immunity at logic low output 4 cm l 25 30 ? kv/s common mode transient immunity at logic high output 4 cm h 25 30 ? kv/s enable to data valid t en1 ?5?ns enable to data tri-state t en2 ?5?ns start-up time 5 t su ?3?s notes: 1. t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 2. t psk is the magnitude of the worst-case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages, and output l oad within the recommended operating conditions. 3. codirectional channel-to-channel matching is the absolute va lue of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 4. cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common-mode voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew rates apply to both rising and falling common -mode voltage edges. the transie nt magnitude is the range over which the common mode is slewed. 5. start-up time is the time period from the a pplication of power to valid data at the output. table 3. electrical characteristics (continued) (v dd1 = 2.5 v, v dd2 = 2.5 v, t a = ?40 to 100 oc) parameter symbol test condition min typ max unit
si8440/41/42/45 rev. 0.51 13 table 4. recommended operating conditions parameter symbol test condition min typ max unit ambient operating temperature* t a 100 mbps, 15 pf, 5 v ?40 25 125 oc 150 mbps, 15 pf, 5 v 0 25 100 oc supply voltage v dd1 2.375 ? 5.5 v v dd2 2.375 ? 5.5 v *note: the maximum ambient temperature is dependent on data freque ncy, output loading, number of operating channels, and supply voltage. table 5. absolute maximum ratings parameter symbol min typ max unit storage temperature t stg ?65 ? 150 oc ambient temperature under bias t a ?40 ? 125 oc supply voltage v dd1 , v dd2 ?0.5 ? 6 v input voltage v i ?0.5 ? v dd + 0.5 v output voltage v o ?0.5 ? v dd + 0.5 v output current drive channel l o ??10ma lead solder temperature (10s) ? ? 260 oc maximum isolation voltage ? ? 4000 v dc note: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to conditions as specified in the oper ational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 6. package characteristics parameter symbol test condition min typ max unit resistance (input-output) 1 r io ?10 12 ? ? capacitance (input-output) 1 c io f=1mhz ? 1.4 ? pf input capacitance 2 c i ?4.0?pf ic junction-to-case thermal resistance jc thermocouple located at center of package ?45?oc/w ic junction-to-air thermal resistance ja ?107?oc/w device power dissipation 3 p d ??250mw notes: 1. device considered a 2-terminal device; pins 1? 8 shorted together and pins 9?16 shorted together. 2. input capacitance is from any input data pin to ground. 3. the si8440-c-is is tested with v dd1 =v dd2 =5.5v, t j =150oc, c l = 15 pf, input a 150 mbps 50% duty cycle square wave.
si8440/41/42/45 14 rev. 0.51 table 7. regulatory information the si84xx have been approved by the organizations listed below. ul 1 csa vde 2 recognized under 1577 component recognition program 1 approved under csa component acceptance notice #5a certified according to din en 60747-5-2 (vde 0884 part 2): 2003- 01 2 basic insulation, 2500 v rms isola- tion voltage reinforced insulation per csa 60950-1-03 and iec 60950-1, maximum working voltage: basic 477 v rms (675 v pk ) reinforced 130 v rms (183 v pk ) basic insulation, 560 v peak file e257455 file 2500035643 file 5006301-4880-0001 notes: 1. in accordance with ul1577, each si84xx is proof tested by applying an insulation test voltage > 3000 v rms for 1 second (current leakage detection limit = 5 a). 2. in accordance with din en 60747-5-2, each si84xx is pr oof tested by applying an insulation test voltage > 1050 v peak for 1 second (partial discharge detection limit = 5 pc ). a ?*? mark branded on the component designates din en 60747-5-2 approval. table 8. insulation and safety-related specifications parameter symbol test condition value unit rated dielectric insu lation voltage 1 minute duration 2500 v rms minimum external air gap (clearance) l(io1) measured from input terminals to out- put terminals, shortest distance through air 7.7 min mm minimum external tracking (creepage) l(io2) measured from input terminals to out- put terminals, shortest distance path along body 8.1 mm minimum internal gap (internal clearance) insulation distance through insulation 0.017 min mm tracking resistance (comparative tracking index) cti din iec 112/vde 0303 part 1 >175 v basic isolation group material group (din vde 0110, 1/89, table 1) iiia
si8440/41/42/45 rev. 0.51 15 figure 3. thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 table 9. din en 60747-5-2 (vde 0884 part 2) insulation characteristics description symbol characteristic unit installation classific ation per din vde 0110 for rated mains voltages < 150 v rms for rated mains voltages < 300 v rms for rated mains voltages < 400 v rms i-iv i-iii i-ii climatic classification 40/125/21 pollution degree (din vde 0110, table 1) 2 maximum working insulation voltage v iorm 560 v peak input to output test voltage, method b1 (v iorm x 1.875 = v pr , 100% production test, t m = 1 sec, partial dis- charge < 5 pc) v pr 1050 v peak input to output test voltage, method a after environmental tests subgroup 1 (v iorm x1.6=v pr , t m = 60 sec, partial discharge < 5 pc) after input and/ or safety test subgroup 2/3 (v iorm x1.2=v pr , t m = 60 sec, partial discharge < 5 pc) v pr 896 672 v peak v peak highest allowable overvoltage (transient overvoltage, t tr = 10 sec) v tr 4000 v peak safety-limiting values (maximum value allowed in the event of a failure; also see the thermal derating curve, figure 3) case temperature safety input, output, or supply current t s i s 150 210 oc ma insulation resistance at t s , v io = 500 v r s >10 9 ? note: this isolator is suitable for basic electrical isolation only wi thin the safety limit data. main tenance of the safety data is ensured by protective circuits. 0 200 150 100 50 200 150 100 50 0 safety-limiting current (ma) 5.5 v 3.6 v 2.75 v 1 3 0 1 2 5 1 1 0 162 25 75 125 175
si8440/41/42/45 16 rev. 0.51 table 10. si84xx truth table (positive logic) vix input 1 enx input 2 vddi state 1 vddo state 1 vox output 1 comments hh or nc 3 powered 4 powered h enabled, normal operation. lh or nc 3 powered powered l x l powered powered hi-z disabled xh or nc 3 unpowered 5 powered l output returns to input state within 1ms of vddi power. x l unpowered powered hi-z disabled x x powered unpowered l output returns to input state within 1s of vddo power if enx is h or nc. outputs return to hi-z within 8 ns of vddo if enx is l. notes: 1. vix and vox are the respective input and output terminals of a given isolator channel (e.g., channel a1, a2, a3, a4, b1, b2, b3, b4). enx is the enable control input located on th e same side as the vox output terminal. vddi and vddo are the power supplies on the input and output side respectively. 2. it is recommended that the enable inputs be connected to an external logic high or low level when the si84xx is operating in noisy environments. 3. no connect (nc) replaces en1 on si8440/ 45. no connect replaces en2 on the si 8445. no connects are not internally connected and can be left floating, tied to vdd, or tied to gnd. 4. "powered" state is defined as 2.375 v < vdd < 5.5 v. 5. "unpowered" state is defined as vdd = 0 v.
si8440/41/42/45 rev. 0.51 17 2. typical performance characteristics figure 4. si8440/45 typical v dd1 supply current vs. data rate 5, 3.3, and 2.5 v operation figure 5. si8440/45 typical v dd2 supply current vs. data rate 5, 3.3, and 2.5 v operation (15 pf load) figure 6. si8441 typical v dd1 supply current vs. data rate 5, 3.3, and 2.5 v operation figure 7. si8441 typical v dd2 supply current vs. data rate 5, 3.3, and 2.5 v operation (15 pf load) figure 8. si8442 typical v dd1 or v dd2 supply current vs. data rate 5, 3.3, and 2.5 v operation (15 pf load) 5 7 9 11 13 15 0 102030405060708090100 data rate (mbps) current (ma) 2.5v 5v 3.3v 5 10 15 20 25 30 0 102030405060708090100 data rate (mbps) current (ma) 2.5v 5v 3.3v 10 12 14 16 18 20 0 102030405060708090100 data rate (mbps) current (ma) 2.5v 5v 3.3v 5 10 15 20 25 30 0 102030405060708090100 data rate (mbps) current (ma) 2.5v 5v 3.3v 5 10 15 20 25 30 0 102030405060708090100 data rate (mbps) current (ma) 2.5v 3.3v 5v
si8440/41/42/45 18 rev. 0.51 figure 9. propagation delay vs. temperature 5 v operation figure 10. propagation delay vs. temperature 3.3 v operation figure 11. propagation delay vs. temperature 2.5 v operation 5 6 7 8 9 10 -40 -20 0 20 40 60 80 100 120 temperature (degrees c) delay (ns) rising edge falling edge 5 6 7 8 9 10 -40-20 0 20406080100120 temperature (degrees c) delay (ns) rising edge falling edge 5 7 9 11 13 15 -40-20 0 20406080100120 temperature (degrees c) delay (ns) falling edge rising edge
si8440/41/42/45 rev. 0.51 19 3. application information 3.1. theory of operation the operation of an si8440 channel is analogous to that of an opto coupler, except an rf carrier is modulated instead of light. this simple archit ecture provides a robust isolated data path and requires no special considerations or initialization at start-up. a simplified block diagram for a single si8440 channel is shown in figure 12. a channel consists of an rf transmit ter and receiver separated by a transformer. referring to the transmitter, input a modulates the carrier provided by an rf oscillator using on/off keying and applies the resulting waveform to the primary of the tran sformer. the receiver contains a demodulator that decodes the input state according to its rf energy content and applies the result to output b via the output driver. figure 12. simplified channel diagram 3.2. eye diagram figure 13 illustrates an eye-diagram taken on an si8440. the test us ed an anritsu (mp1763c) pulse pattern generator for the data source. the output of the generator's clock and data from an si8440 were captured on an oscilloscope. the resu lts illustrate that data integrit y was maintained even at the hi gh data rate of 150 mbps. the results also show that very low pulse width distortion and very little jitter were exhibited. figure 13. eye diagram transmitter receiver rf oscillator modulator demodulator a b
si8440/41/42/45 20 rev. 0.51 4. layout recommendations dielectric isolation is a set of specific ations produced by the safety regulatory agencies from around the world that describes the physical construction of electrical equipment that derives power from a high-voltage power system such as 100?240 v ac systems or industrial power systems. the dielec tric test (or hipot test) given in the safety specifications places a very high voltage between the input power pins of a product an d the user circuits and the user touchable surfaces of the product. for the iec rela ting to products deriving their power from the 220?240 v power grids, the test voltage is 2500 v ac (or 3750 v dc ?the peak equivalent voltage). there are two terms described in the safety specifications: creepage?the distance along the insulating surface an arc may travel. clearance?the distance through the shortest path through air that an arc may travel. figure 14 illustrates the accepted met hod of providing the pro per creepage distance along the surface. for a 220?240 v application, this distance is 8 mm and the wid e body soic package must be used. there must be no copper traces within this 8 mm exclusion area, and the surface should have a confor mal coating such as solder resist. the digital isolator chip must straddle this exclusion area. figure 14. creepage distance 4.1. supply bypass the si844x requires a 0.1 f bypass capacitor between v dd1 and gnd1 and v dd2 and gnd2. the capacitor should be placed as close as possible to the package. 4.2. input and out put characteristics the si844x inputs and outputs are standard cmos drivers/receivers.
si8440/41/42/45 rev. 0.51 21 4.3. enable inputs enable inputs en1 and en2 can be used for multiplexing, for clock sync, or other outp ut control. en1, en2 logic operation is summarized for each isolator product in tabl e 11. these inputs are internally pulled-up to local vdd by a 9 a current source allowing them to be connected to an external logic level (high or low) or left floating. to minimize noise coupling, do not connect circuit traces to en1 or en2 if they are left floating. if en1, en2 are unused, it is recommended they be connec ted to an external logic level, especi ally if the si84xx is operating in a noisy environment. table 11. enable input truth table p/n en1 en2 operation si8440 ? h outputs b1, b2, b3, b4 are enabled. ? l outputs b1, b2, b3, b4 are disabled and in high impedance state. si8441 h x output a4 enabled. l x output a4 disabled and in high impedance state. x h outputs b1, b2, b3 are enabled. x l outputs b1, b2, b3 are disabled and in high impedance state. si8442 h x outputs a3 and a4 are enabled. l x outputs a3 and a4 are disabled and in high impedance state. x h outputs b1 and b2 are enabled. x l outputs b1 and b2 are disabled and in high impedance state. si8445 ? ? outputs b1, b2, b3, b4 are enabled.
si8440/41/42/45 22 rev. 0.51 4.4. rf immunity and comm on mode transient immunity the si8440 family has very high common mode transient immunity while transmitting data. this is typically measured by applying a square pulse with very fast ri se/fall times between the isolated grounds. measurements show no failures up to 30 kv/s. during a high surge even t the output may glitch low for up to 20?30 ns, but the output corrects immediately after the surge event. the si844x family passes the industrial requirements of cispr24 for rf immunity of 3 v/m using an unshielded evaluation board. as shown in figure 15, the isolated ground planes form a parasitic dipole antenna, while figure 16 shows the rms common mode voltage versus frequency above which the si844x becomes susceptible to data corruption. to avoid compromising data, care must be taken to keep rf common-mode voltage below the envelope specified in figure 16. the pcb should be laid-out to not act as an efficient antenna for the rf frequency of interest. rf su sceptibility is also significantly reduced when the e nd system is housed in a metal enclosure, or otherwise shielded. figure 15. dipole antenna figure 16. rms common mode voltage vs. frequency isolator gnd1 gnd2 dipole antenna 0 1 2 3 4 5 500 1000 1500 2000 frequency (mhz) rms voltage (v)
si8440/41/42/45 rev. 0.51 23 4.5. rf radiated emissions the si8440 family uses a rf carrier frequency of appro ximately 2.1 ghz. this will re sult in a small amount of radiated emissions at this frequency and its harmonics. the radiation is not from the ic chip but due to a small amount of rf energy driving the isolated grou nd planes which can act as a dipole antenna. the unshielded si8440 evaluation board passes f cc requirements. table 12 shows measured emissions compared to fcc requirements. radiated emissions can be reduced if the circuit board is enclosed in a shielded enclosure or if the pcb is a less efficient antenna. table 12. radiated emissions frequency (ghz) measured (dbv/m) fcc spec (dbv/m) compared to spec (db) 2.094 70.0 74.0 ?4.0 2.168 68.3 74.0 ?5.7 4.210 61.9 74.0 ?12.1 4.337 60.7 74.0 ?13.3 6.315 58.3 74.0 ?15.7 6.505 60.7 74.0 ?13.3 8.672 45.6 74.0 ?28.4
si8440/41/42/45 24 rev. 0.51 5. pin descriptions name soic-16 pin# type description v dd1 1 supply side 1 power supply. gnd1 2 ground side 1 ground. a1 3 digital input side 1 digital input. a2 4 digital input side 1 digital input. a3 5 digital i/o side 1 digital input or output. a4 6 digital i/o side 1 digital input or output. en1/nc* 7 digital input side 1 active high enable. nc on si8440/45. gnd1 8 ground side 1 ground. gnd2 9 ground side 2 ground. en2/nc* 10 digital input side 2 active high enable. nc on si8445. b4 11 digital i/o side 2 digital input or output. b3 12 digital i/o side 2 digital input or output. b2 13 digital output side 2 digital output. b1 14 digital output side 2 digital output. gnd2 15 ground side 2 ground. v dd2 16 supply side 2 power supply. *note: no connect. these pins are not internally connected. they can be left floating, tied to v dd or tied to gnd. wide body soic v dd1 gnd1 a1 a3 a4 en1/nc gnd1 a2 1 2 3 4 5 6 7 8 top view v dd2 gnd2 b2 b1 b4 b3 gnd2 en2/nc 9 12 11 10 13 14 15 16
si8440/41/42/45 rev. 0.51 25 6. ordering guide ordering part number number of inputs v dd1 side number of inputs v dd2 side maximum data rate temperature package type si8440-a-is 4 0 1 ?40 to 125 c soic-16 si8440-b-is 4 0 10 ?40 to 125 c soic-16 si8440-c-is 4 0 150 ?40 to 125 c soic-16 si8441-a-is 3 1 1 ?40 to 125 c soic-16 si8441-b-is 3 1 10 ?40 to 125 c soic-16 si8441-c-is 3 1 150 ?40 to 125 c soic-16 si8442-a-is 2 2 1 ?40 to 125 c soic-16 si8442-b-is 2 2 10 ?40 to 125 c soic-16 si8442-c-is 2 2 150 ?40 to 125 c soic-16 si8445-b-is 4 0 10 ?40 to 125 c soic-16 note: all packages are pb-free and rohs compliant. moisture sens itivity level is msl2 with pe ak reflow temperature of 260 c according to the jedec industry standard cl assifications, and peak solder temperature.
si8440/41/42/45 26 rev. 0.51 7. package outline: wide body soic figure 17 illustrates the package details for the quad -channel digital isolator. tabl e 14 lists the values for the dimensions shown in the illustration. figure 17. 16-pin wide body soic table 14. package diagram dimensions symbol millimeters min max a ? 2.65 a1 0.1 0.3 d 10.3 bsc e 10.3 bsc e1 7.5 bsc b 0.31 0.51 c 0.20 0.33 e 1.27 bsc h 0.25 0.75 l 0.4 1.27 0 7
si8440/41/42/45 rev. 0.51 27 d ocument c hange l ist revision 0.2 to revision 0.3 added enable high and low typical current specifications to tables 1, 2, and 3. added startup time specifications (with note 5) to tables 1, 2, and 3. rewrote paragraph 1 in section "4.4. rf immunity and common mode transient immunity" on page 22 to reflect 30kv/s transi ent immunity capability. revision 0.3 to revision 0.4 added minimum and maximum values to the 5.0 v, 3.3 v, and 2.5 v electrical specifications in table 1, table 2, and table 3, respectively. revision 0.4 to revision 0.5 updated block diagram on page 1. added si8445 to various tables. updated table 6, ?package characteristics,? on page 13. updated table 7, ?regulatory information,? on page 14. updated table 9, ?din en 60747-5-2 (vde 0884 part 2) insulation characteristics,? on page 15. updated figure 3, ?thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2,? on page 15. added table 10, ?si84xx truth table (positive logic),? on page 16. added table 11, ?enable input truth table,? on page 21. revision 0.5 to revision 0.51 added nc note (note 3) to table 10, ?si84xx truth table (positive logic),? on page 16. added nc note (*) to "5. pin descriptions" on page 24.
si8440/41/42/45 28 rev. 0.51 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: powerproducts@silabs.com internet: www.silabs.com silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon labor atories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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